Intel Advanced Packaging for Bigger AI Chips

This week at the EEEE Electronic Components and Packaging Technology conference, Intel has unveiled that it is developing a new technology for catching flea which will allow greater processors for AI.

With the slowdown in Moore’s law, advanced GPU manufacturers and other chips of data centers must add more silicon zone to their products to follow the incessant rise in IA IT needs. But the maximum size of a single silicon chip is fixed at around 800 square millimeters (with one exception), the manufacturers therefore had to turn to advanced packaging technologies which integrate several pieces of silicon in a way that allows them to act as a single chip.

Three of the innovations that Intel unveiled at ECTC aimed at attacking the limitations in the quantity of silicon that you can involve in a single package and the size of this package. They include improvements to the technology that Intel uses to connect adjacent silicon together, a more precise method for the link of silicon to the package substrate and a system to extend the size of a critical part of the whole that eliminates heat. Together, technologies allow the integration of more than 10,000 square millimeters of silicon in a set which can be greater than 21,000 mm²—A massive area the size of four and a half credit cards.

EMIB obtains a 3D upgrade

One of the limits of the quantity of silicon can hold in a single package concerns the connection of a large number of silicon matrices on their edges. The use of an organic polymer package substrate to interconnect silicon matrices is the most affordable option, but a silicon substrate allows you to create more dense connections on these edges.

Intel’s solution, introduced over five years ago, is to integrate a small silicon tape into the organic packaging under the adjacent edges of silicon matrices. This silicon tape, called EMIB, is engraved with fine interconnections that increase the density of connections beyond the organic substrate can manage.

In ECTC, Intel revealed the latest torsion of EMIB technology, called EMIB-T. In addition to the usual fine horizontal interconnections, EMIB-T provides relatively thick vertical copper connections called VIAS through silicon, or TSV. The TSVs allow the supply of the circuit card printed below to connect directly to the chips above instead of having to move around the EMIB, reducing the lost power by a longer journey. In addition, the EMIB-T contains a copper grid which acts as a mass plan to reduce noise in the power delivered due to the process nuclei and other circuits suddenly accelerating their workloads.

“It seems simple, but it is a technology that brings us a lot of capacity,” explains Rahul Manepalli, vice-president of the substrate packaging technology at Intel. With him and the other technologies described by Intel, a customer could connect the silicon equivalent to more than 12 full -size silicon matrices – 10,000 mm² of silicon – in a single packaging using 38 EMIB -T or more bridges.

Thermal control

Another technology indicated at the ECTC which helps increase the size of the packages is the thermal compression link with low thermal content. It is a variant of the technology used today to attach silicon matrices to organic substrates. The micro -meter -scale welding bumps are positioned on the substrate where they will connect to a silicon matrix. The sector is then heated and leaning on the microbumps, melting them and connecting the interconnections of the silicon package.

Because silicon and substrate expand at different rates when heated, engineers must limit the distance or inter-bump. In addition, the difference in expansion makes it difficult to make very large substrates full of many silicon matrices, which is the direction that AI processors need.

The new Intel technology makes the inadequacy of the thermal extension more predictable and manageable, explains Manepalli. The result is that very large substrates can be populated by matrices. Alternatively, the same technology can be used to increase the density of EMIB connections to approximately one every 25 micrometers.

A flattest spreader

These larger silicon assemblies will generate even more warmth than today’s systems. It is therefore essential that the heat route out of silicon is not obstructed. An integrated piece of metal called a heat spreader is the key to this, but making a fairly large for these large packages is difficult. The packaging substrate can be deformed, and the metallic heat spreader itself may not remain perfectly flat, so it may not touch the top of the hot matrices from which it is supposed to suck the heat. Intel’s solution was to assemble the heat spreader integrated into parts rather than a single room. This allowed the company to add additional stiffening components, among other things, to maintain any flat and in place.

“Keeping it flat at higher temperatures is a great advantage for reliability and yield,” explains Manepalli.

Intel says that technologies are still in the R&D phase and would not comment when these technologies would make its commercially debut. However, they will probably have to arrive in the coming years so that the Intel Foundry rivals with the planned expansion of TSMC packaging.